Xilinx XC2C64A CoolRunner-II CPLD Dev Board (Reset Glitch)

Product Code: CoolRunner
Availability: In Stock

We have the 360 SPI NAND Flasher available for your to dump the NAND content.


The following components are installed on this board:

  • Caps: 220pF, 100nF
  • Resistors: 1K, 22K
  • Diodes: 3 x 1N4148
  • Trimmers (adjustable cap, to adjust glitch for Slim): 30pF x 2, so the capacitance for slim can be adjusted between 220pf - 280pf

If you have parallel port on your PC, we recommend this item as well: Parallel JTAG Utility Bundle (Read 360 NAND and Program XC2C64A via Parallel Port) It allows you to read the NAND flash needed for RGH, it also can be used for programming our XC2C64A CPLD Dev board.

The is JTAG adapter can also be used for debricking wireless routers, cable modem mods, etc.

Supported by zJTAG, Xilinx iMPACT. However if you do not have parallel port, we suggest the following two items: USB SPI JTAG Utility Bundle with Solderless Flasher Addon - for your to read and flash NAND using USB port. TUMPA - Program XC2C64A by USB - a Multi Protocol USB JTAG adapter to program XC2C64A CPLD, debrick routers, mod cable modems. Supported by zJTAG, XC2SPROG and more. We have tutorial on how to program RGH board with this adapter. Check our tutorial wiki. No need to solder the resistors, caps or diodes!

Works for both phat and slim.

What's in the package:

  • TIAO Xilinx XC2C64A CoolRunner-II CPLD Dev Board with trinity.jed pre-flashed
  • 4 pieces female to female flexible wires, (cut in half, insert one end to dev board, solder another end to your device)

We also have the following programmers available for this device: TIAO USB Multi-Protocol Adapter TIAO Universal JTAG Programmer

Tutorials and instructions are on our wiki site: TIAO Wiki

The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications.

This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of four Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

  • Optimized for 1.8V systems - As fast as 4.6 ns pin-to-pin logic delays - As low as 15 μA quiescent current
  • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V
Advanced system features
  • Fastest in system programming - 1.8V ISP using IEEE 1532 (JTAG) interface
  • EEE1149.1 JTAG Boundary Scan Test 
  • Optional Schmitt-trigger input (per pin)
  • Two separate I/O banks 
  • RealDigital 100% CMOS product term generation 
  • Flexible clocking modes
  • Optional DualEDGE triggered registers 
  • Global signal options with macrocell control 
  • Multiple global clocks with phase selection per macro-cell 
  • Multiple global output enables 
  • Global set/reset
  • Efficient control term clocks, output enables, and set/resets for each macrocell and shared across function blocks 
  • Advanced design security
  • Optional bus-hold, 3-state, or weak pullup on selected I/O pins 
  • Open-drain output option for Wired-OR and LED drive
  • Optional configurable grounds on unused I/Os 
  • Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels 
  • PLA architecture
  • Superior pinout retention 
  • 100% product term routability across function block
  • Hot pluggable

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